Difference between revisions of "Bit clock"
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Due to the fact that the Word Clock format is a relatively "low frequency" signal compared to the serial formats, with two transitions per sample period as versus hundreds of transitions per sample period; the Word Clock signal does offer advantages in terms of [[jitter]] issues. With reasonable care to use of the proper cable and [[termination]]; cable reflections (one of the main sources of jitter) have the time to decay before the next transition occurs; which is not the case with serial formats. | Due to the fact that the Word Clock format is a relatively "low frequency" signal compared to the serial formats, with two transitions per sample period as versus hundreds of transitions per sample period; the Word Clock signal does offer advantages in terms of [[jitter]] issues. With reasonable care to use of the proper cable and [[termination]]; cable reflections (one of the main sources of jitter) have the time to decay before the next transition occurs; which is not the case with serial formats. | ||
| − | Technology advanced; and as the speed of circuitry increased it became commonplace for digital systems to use high-speed serial transmission with the obvious advantage of fewer conductors needed to move the data from device to device. As wordlength increased from 16, to 32, to 64 bits; the advantages of serial transmission became even greater. Contemporary digital audio equipment commonly uses serial data transmission internally as well as externally; and this makes it necessary to have an internal bit clock which is in the range of 62 to 128 times the sample frequency. | + | Technology advanced; and as the speed of circuitry increased it became commonplace for digital systems to use high-speed [[serial]] transmission with the obvious advantage of fewer conductors needed to move the data from device to device. As wordlength increased from 16, to 32, to 64 bits; the advantages of serial transmission became even greater. Contemporary digital audio equipment commonly uses serial data transmission internally as well as externally; and this makes it necessary to have an internal bit clock which is in the range of 62 to 128 times the sample frequency. |
| − | Digital audio formats designed explicitly for transmission between pieces of equipment have an "embedded" bit clock as part of the electrical waveform, and the coding of the electrical waveform allows for these very high frequency signals to be transmitted with [[signal | + | Digital audio formats designed explicitly for transmission between pieces of equipment have an "embedded" bit clock as part of the electrical waveform, and the coding of the electrical waveform allows for these very high frequency signals to be transmitted with [[signal transformer]]s; which allows them to work properly. '''Formats like I2s do not have the means to address serious issues that arise when transmitting very high frequency signals more than short distance because it requires DC transmission.''' The discussion of these issues is beyond the scope of this subject. |
==Basics== | ==Basics== | ||
Bit clock signals are used in serial digital audio formats like [[I2S]] as a means of synchronizing the transmission of signals from one IC to another on the same PC board. The serial audio data may be broken into separate left and right channel data streams; or as in the case of I2S, may be combined into one stream in an alternating "left-right" manner. In either case; the bit clock has one cycle per bit of information in the serial data stream; with either the "rising edge" or "falling edge" of the bit clock marking the beginning of each "bit" in the serial data. In the case of left-right data, a "left-right" clock is also required to determine which channel's information is being received. | Bit clock signals are used in serial digital audio formats like [[I2S]] as a means of synchronizing the transmission of signals from one IC to another on the same PC board. The serial audio data may be broken into separate left and right channel data streams; or as in the case of I2S, may be combined into one stream in an alternating "left-right" manner. In either case; the bit clock has one cycle per bit of information in the serial data stream; with either the "rising edge" or "falling edge" of the bit clock marking the beginning of each "bit" in the serial data. In the case of left-right data, a "left-right" clock is also required to determine which channel's information is being received. | ||
| − | This "left-right" clock signal is sometimes referred to as "Word Clock;" but is not exactly the same as the [[Word Clock]] signal used for synchronization of digital audio equipment. It is similar because it is it has one cycle for every [[sample period]] of digital audio signal, and in serial formats like [[AES3]] and [[S-PDIF]] it was originally specified as corresponding to the serial data with the “positive” half cycle denoting the left channel and the “negative” half cycle the right channel. But in early implementations of the AES interface channel reversals sometimes occurred due to slight [[phase]] differences between the Word Clock signal and an AES data stream which did not implement the left-right channel status bit. As a result | + | This "left-right" clock signal is sometimes referred to as "Word Clock;" but is not exactly the same as the [[Word Clock]] signal used for synchronization of digital audio equipment. It is similar because it is it has one cycle for every [[sample period]] of digital audio signal, and in serial formats like [[AES3]] and [[S-PDIF]] it was originally specified as corresponding to the serial data with the “positive” half cycle denoting the left channel and the “negative” half cycle the right channel. But in early implementations of the AES interface channel reversals sometimes occurred due to slight [[phase]] differences between the Word Clock signal and an AES data stream which did not implement the left-right channel status bit. As a result most contemporary AES interfaces rely on the left-right channel status bits to determine the correct channel status. |
Please see [[serial data]] more information. | Please see [[serial data]] more information. | ||
Latest revision as of 16:45, 3 August 2017
Overview
The term "bit clock" is used to describe a one cycle per sample "square wave" signal used for internal synchronization within digital audio equipment. One example of such a system is the I2S format used for transmission of digital audio information from one IC to another on a PC board.
History
Earlier digital audio systems employed a number of formats of interconnection, many of which were proprietary. Some were parallel; in which case each bit was carried on a separate conductor and a Word Clock signal was used to synchronize the timing of the transmission of each complete word of 16 bits, once per sample period.
Due to the fact that the Word Clock format is a relatively "low frequency" signal compared to the serial formats, with two transitions per sample period as versus hundreds of transitions per sample period; the Word Clock signal does offer advantages in terms of jitter issues. With reasonable care to use of the proper cable and termination; cable reflections (one of the main sources of jitter) have the time to decay before the next transition occurs; which is not the case with serial formats.
Technology advanced; and as the speed of circuitry increased it became commonplace for digital systems to use high-speed serial transmission with the obvious advantage of fewer conductors needed to move the data from device to device. As wordlength increased from 16, to 32, to 64 bits; the advantages of serial transmission became even greater. Contemporary digital audio equipment commonly uses serial data transmission internally as well as externally; and this makes it necessary to have an internal bit clock which is in the range of 62 to 128 times the sample frequency.
Digital audio formats designed explicitly for transmission between pieces of equipment have an "embedded" bit clock as part of the electrical waveform, and the coding of the electrical waveform allows for these very high frequency signals to be transmitted with signal transformers; which allows them to work properly. Formats like I2s do not have the means to address serious issues that arise when transmitting very high frequency signals more than short distance because it requires DC transmission. The discussion of these issues is beyond the scope of this subject.
Basics
Bit clock signals are used in serial digital audio formats like I2S as a means of synchronizing the transmission of signals from one IC to another on the same PC board. The serial audio data may be broken into separate left and right channel data streams; or as in the case of I2S, may be combined into one stream in an alternating "left-right" manner. In either case; the bit clock has one cycle per bit of information in the serial data stream; with either the "rising edge" or "falling edge" of the bit clock marking the beginning of each "bit" in the serial data. In the case of left-right data, a "left-right" clock is also required to determine which channel's information is being received.
This "left-right" clock signal is sometimes referred to as "Word Clock;" but is not exactly the same as the Word Clock signal used for synchronization of digital audio equipment. It is similar because it is it has one cycle for every sample period of digital audio signal, and in serial formats like AES3 and S-PDIF it was originally specified as corresponding to the serial data with the “positive” half cycle denoting the left channel and the “negative” half cycle the right channel. But in early implementations of the AES interface channel reversals sometimes occurred due to slight phase differences between the Word Clock signal and an AES data stream which did not implement the left-right channel status bit. As a result most contemporary AES interfaces rely on the left-right channel status bits to determine the correct channel status.
Please see serial data more information.